This invention relates generally to integrated circuit packaging incorporating a high density interconnect structure, and more particularly to packaging high speed devices having sensitive structures such as air bridge structures, with a protective material, which after lamination and formation of the high density interconnect structure, may be left in place. This leaves the air bridge protected, and its performance negligibly affected, without requiring removal of modification of the high density interconnect structure.
In the fabrication of certain multi-chip module (MCM) circuits, high performance is accomplished by the use of high speed gallium arsenide (GaAs) devices having delicate structures which can easily be damaged or destroyed during fabrication. These include conductors which are spaced from the surface of the GaAs by an air gap--a structure which is known as an air bridge. Air bridges are used in these circuits to provide improved signal propagation and reduced capacitive coupling over that possible with conventional chip wiring.
The interconnect structure used in the fabrication of high density interconnect (HDI) circuits has many advantages in the compact assembly of MCMs. For example, a multi-chip electronic system (such as a microcomputer incorporating 30-50 chips) can be fully assembled and interconnected by a suitable HDI structure on a single substrate, to form a unitary package which is 2 inches long by 2 inches wide by 0.050 inches thick. Even more important, the interconnect structure can be disassembled from the substrate for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where many (e.g., 50) chips, each being very costly, may be incorporated in a single system on one substrate. This repairability feature is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 50-100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but may be made larger or smaller. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. The cavity bottom may be made respectively deeper or shallower at a location where a particularly thick or thin component will be placed, so that the upper surface of the corresponding component is in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer, which may preferably be a polyetherimide resin (such as ULTEM.RTM. 6000 resin, available from the General Electric Company, Fairfield, Conn.), or an adhesive composition such as is described in U.S. Pat. No. 5,270,371, herein incorporated in its entirety by reference. The various components are then placed in their desired locations within the cavity and the entire structure is heated to remove solvent and thermoplastically bond the individual components to the substrate.
Thereafter, a film (which may be KAPTON.RTM. polyimide, available from E.I. du Pont de Nemours Company, Wilmington, Del.), of a thickness of approximately 0.0005-0.003 inches (approx. 12.5-75 microns), is pretreated by reactive ion etching (RIE) to promote adhesion. The substrate and chips must then be coated with ULTEM.RTM. 1000 polyetherimide resin or another thermoplastic adhesive to adhere the KAPTON.RTM. resin film when it is laminated across the tops of the chips, any other components and the substrate. Thereafter, via holes are provided (preferably by laser drilling) through the KAPTON.RTM. resin film, and ULTEM.RTM. resin layers, at locations in alignment with the contact pads on the electronic components to which it is desired to make contact. A multi-sublayer metallization layer, with a first sublayer comprising titanium (approximately 1000 .ANG.) and a second layer comprising copper (approximately 2000 .ANG.), is sputter deposited over the KAPTON.RTM. resin layer and extends into the via holes to make electrical contact to the contact pads disposed thereunder. The sputtered copper provides a seed layer for copper electroplating (3 to 4 microns thick). A final layer of titanium (1000 .ANG.) is sputter deposited to complete the Ti/Cu/Ti multilayer metallization. This metallization layer is patterned to form individual conductors using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Alternatively, exposure through a mask may be used.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the patents and applications listed hereinafter.
This high density interconnect structure provides many advantages. Included among these are the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant, advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require the prepackaging of each semiconductor chip, the design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities may be formed in an already fired ceramic substrate by conventional or laser milling. This process is straight-forward and fairly rapid with the result that once a desired configuration of the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips in as little as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 5,127,998, entitled "Area-Selective Metallization Process" by H. S. Cole et al.; U.S. Pat. No. 5,127,844, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. Pat. No. 5,169,678, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; and U.S. Pat. No. 5,108,825, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al; U.S. application Ser. No. 07/987,849, entitled "Plasticized Polyetherimide Adhesive Composition and Usage" by Lupinski et al. Each of these Patents and Patent Applications, including the references contained therein, is hereby incorporated in its entirety by reference.
This high density interconnect structure has been developed for use in interconnecting semiconductor chips to form digital systems. That is, for the connection of systems whose operating frequencies are typically less than about 50 MHz, which is low enough that transmission line, other wave impedance matching and dielectric loading effects have not needed to be considered.
The interconnection of structures or devices intended to operate at very high frequencies presents many challenges not faced in the interconnection of digital systems. For example, use of gigahertz frequencies requires consideration of wave characteristics, transmission line effects and material properties. Also, use of high frequencies requires the consideration of the presence of exposed delicate structures on MCMs and other components and system and component characteristics which do not exist at the lower operating frequencies of such digital systems. These considerations include the question of whether the dielectric materials are suitable for use at gigahertz frequencies, since materials which are good dielectrics at lower frequencies can be quite lossy or even conductive at high frequencies. Further, even if the dielectric is not lossy at gigahertz frequencies, its dielectric constant itself may be high enough to unacceptably modify the operating characteristics of MCMs or air bridges.
As stated above, the interconnect structure used in the fabrication of HDI circuits is created from alternating layers of laminated dielectric films and patterned metal films. In the process of laminating the dielectric layers, the adhesive used to bond the dielectric layers is caused to flow and form a quality, void-free interface. There is a substantial concern that air bridges and other sensitive structures may be modified, damaged or destroyed by the lamination pressure. Also, these sensitive structures may be overlay sensitive, i.e., the operating characteristics of the device or component may be different when the device or component is free of interconnection dielectric material than when these devices have high density interconnect dielectric layers disposed over them. Lamination as well as other processing steps may also cause the thermoplastic adhesive to infiltrate the air gap under the conductor, thereby modifying the dielectric properties of that gap.
Since there are sensitive structures present, low temperature processing is needed to ensure that these structures are not damaged during multi-chip module fabrication. For example, chips of certain semiconductors (GaAs, InSb and HgCdTe), as well as the structures on these chips, e.g., air bridges, are very sensitive to processing in high temperature regimes. Multichip modules incorporating a high density interconnect structure, as well as sensitive structures, must be fabricated at temperatures below about 260.degree. C.
To maintain the performance advantage of having air, or some other electrical insulator, as the dielectric medium, the MCM fabrication process must be designed to provide a means of preserving these air bridge structures from intrusion by other materials.
For example, related application Ser. No. 07/869,090 filed on Apr. 14, 1992, by W. P. Kornrumpf et al., and entitled, "High Density Interconnected Microwave Circuit Assembly" teaches removing the high density interconnect dielectric from portions of the chip which are overlay sensitive. That is, after the HDI structure is laminated, the portion of the HDI structure overlying the sensitive structure is removed by ablation. Removing the HDI structure improves the performance of the sensitive structure, e.g., air bridge, because there is no overlying material. However, ablating the overlying material does not prevent adhesive from flowing under the bridge during processing; nor does it prevent the lamination pressure from occasionally damaging or even collapsing the air bridge. As will be discussed hereinbelow, removing the HDI structure over the sensitive structure also decreases the area available for routing the electrical conductors within the HDI structure and severely restricts the potential usefulness of the HDI technique. This patent application, including the references contained therein, is hereby incorporated in its entirety by reference.
Related U.S. Pat. No. 5,331,203, filed Apr. 5, 1990, by Wojnarowski et al., and entitled "A High Density Interconnect Structure Including a Chamber" teaches bonding the chip containing a sensitive structure into a deep chip-well. Since the chip-well is deeper than the chip is thick, there is a space created over the surface of the chip. A first dielectric layer is laminated such that this layer is only attached to a plateau portion of the substrate and to the upper surface of the chip. This first dielectric layer is not applied over the sensitive structure. Then, the remainder of the HDI structure is laminated, thereby creating a "chamber" of air over the sensitive structure. If successfully laminated, this technique creates a space over the sensitive structure to allow it to work properly. However, in practice this lamination procedure is very difficult to reproduce without damaging the sensitive structure. Because the second dielectric layer has adhesive, it is still difficult to produce a module where the adhesive from this layer does not infiltrate the space under the air bridge. Furthermore, because the chip is in a deep chip-well it is difficult to ake electrical contact with the chip pads through the via holes with the metallization layer within the high density interconnect structure. This patent application, including the references contained therein, is hereby incorporated in its entirety by reference.
Related application Ser. No. 07/546,965, filed Jul. 2, 1990, by Cole et al, and entitled "High Density Interconnection Including a Spacer and a Gap", teaches applying spacers over the contact pads present on the integrated circuit chips, and then stretching the first HDI dielectric layer over these spacers such that the dielectric layer does not contact the chip surface. This application provides a method of fabricating a HDI module incorporating a sensitive chip structure without the dielectric layer of the high density interconnect structure inhibiting the chip's performance. However, since the adhesive from the first dielectric layer is designed to flow and form a void free layer, it may contaminate any sensitive structure which is placed between the spacers. Also, because the high density interconnect structure is supported only by the spacers, there may be difficulties with the dielectric layers sagging and causing interruptions in the metallization layers. This patent application, including the references contained therein, is hereby incorporated in its entirety by reference.
Related application Ser. No. 08/046,299, entitled "High Density Interconnection of Substrates and Integrated Circuit Chips containing Sensitive Structures", to Cole et al. teaches laying down a solvent soluble layer to "protect" the air bridge during lamination of the HDI structure. Once the module is fully worked-up, the HDI structure which overlays the sensitive structure is ablated away and the module is immersed in a solvent to remove the protective layer. This method, although very labor intensive, inhibits damage to the air bridge and prohibits the adhesive from getting under the bridge during lamination of the high density interconnect structure. This patent application, including the references contained therein, is hereby incorporated in its entirety by reference.
Unfortunately, the teaching disclosed in the last-mentioned application suffers from the disadvantage that the need to exclude the high density interconnect structure from the surface of overlay-sensitive components severely restricts the surface area available for the routing of the high density interconnect structure metallization layers since they cannot be routed over the area from which the dielectric layer is to be removed. Where chips are closely packed for maximum density, this essentially limits the high density interconnect structure to the routing of conductors in the "streets" and "avenues" portion of the structure which extends from the contact pads of one chip to the contact pads of the adjacent chip. For systems where high density of interconnect conductors is required, such a restriction can require excessive numbers of layers of interconnect conductors, require that the chips be spaced further apart than would otherwise be necessary, or even make a system unroutable.
Consequently, an improved method for protecting sensitive structures which does not disrupt the routing of the metallization layers within the high density interconnect structure, is desirable.